SI8261AAC-C-IS Datasheet, PDF (16/40 Pages) Silicon Laboratories – 5 KV LED EMULATOR INPUT, 4.0 A ISOLATED GATE DRIVERS

Si826x
4.3. Under Voltage Lockout (UVLO)
The UVLO circuit unconditionally drives V_O low when V_DD is below the lockout threshold. Referring to Figures 11
through 13, upon power up, the Si826x is maintained in UVLO until VDD rises above VDD_UV+. During power down,
the Si826x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDD_UV+ –
VDD_HYS).
VDDUV+ (Typ)
VDDUV+ (Typ)
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
Supply Voltage (V_DD - GND) (V)
Figure 11. Si826xxAx UVLO Response (5 V)
VDDUV+ (Typ)
9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0
Supply Voltage (V_DD - GND) (V)
Figure 13. Si826xxCx UVLO Response (12 V)
6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
Supply Voltage (V_DD - GND) (V)
Figure 12. Si826xxBX UVLO Response (8 V)
16
Rev. 1.3