C161V_96 Datasheet, PDF (98/260 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:19h
Parallel Ports / C161
When an external bus mode is enabled, the direction of the port pin and the loading of data into the
port output latch are controlled by the bus controller hardware. The input of the port output latch is
disconnected from the internal bus and is switched to the line labeled “Alternate Data Output” via a
multiplexer. The alternate data can be the 16-bit intrasegment address or the 8/16-bit data
information. The incoming data on PORT0 is read on the line “Alternate Data Input”. While an
external bus mode is enabled, the user software should not write to the port output latch, otherwise
unpredictable results may occur. When the external bus modes are disabled, the contents of the
direction register last written by the user becomes active.
The figure below shows the structure of a PORT0 pin.
y = 7...0
Figure 6-4
Block Diagram of a PORT0 Pin
Semiconductor Group
6-6