C161V_96 Datasheet, PDF (138/260 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:19h
The External Bus Interface / C161
Bit
MCTC
RWDCx
MTTCx
BTYP
ALECTLx
BUSACTx
CSRENx
CSWENx
Function
Memory Cycle Time Control (Number of memory cycle time wait states)
0 0 0 0 : 15 waitstates (Number = 15 - <MCTC>)
...
1 1 1 1 : No waitstates
Read/Write Delay Control for BUSCONx
‘0’: With read/write delay: activate command 1 TCL after falling edge of ALE
‘1’: No read/write delay: activate command with falling edge of ALE
Memory Tristate Time Control
‘0’: 1 waitstate
‘1’: No waitstate
External Bus Configuration
0 0 : 8-bit Demultiplexed Bus
0 1 : 8-bit Multiplexed Bus
1 0 : 16-bit Demultiplexed Bus
1 1 : 16-bit Multiplexed Bus
Note: For BUSCON0 BTYP is defined via PORT0 during reset.
ALE Lengthening Control
‘0’: Normal ALE signal
‘1’: Lengthened ALE signal
Bus Active Control
‘0’: External bus disabled
‘1’: External bus enabled (within the respective address window, see ADDRSEL)
Read Chip Select Enable
‘0’: The CS signal is independent of the read command (RD)
‘1’: The CS signal is generated for the duration of the read command
Write Chip Select Enable
‘0’: The CS signal is independent of the write command (WR,WRL,WRH)
‘1’: The CS signal is generated for the duration of the write command
Semiconductor Group
8-18