C161V_96 Datasheet, PDF (143/260 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:19h
The External Bus Interface / C161
8.4 EBC Idle State
When the external bus interface is enabled, but no external access is currently executed, the EBC
is idle. As long as only internal resources (from an architecture point of view) like IRAM, GPRs or
SFRs, etc. are used the external bus interface does not change (see table below).
Accesses to on-chip X-Peripherals are also controlled by the EBC. However, even though an X-
Peripheral appears like an external peripheral to the controller, the respective accesses do not
generate valid external bus cycles.
Due to timing constraints address and write data of an XBUS cycle are reflected on the external bus
interface (see table below). The „address“ mentioned above includes PORT1, Port 4, BHE and ALE
which also pulses for an XBUS cycle. The external CS signals on Port 6 are driven inactive (high)
because the EBC switches to an internal XCS signal.
The external control signals (RD and WR or WRL/WRH if enabled) remain inactive (high).
Status of the external bus interface during EBC idle state:
Pins
PORT0
Internal accesses only
Tristated (floating)
PORT1
Port 4
Port 6
BHE
ALE
RD
WR/WRL
WRH
Last used external address
(if used for the bus interface)
Last used external segment address
(on selected pins)
Active external CS signal
corresponding to last used address
Level corresponding to last external
access
Inactive (low)
Inactive (high)
Inactive (high)
Inactive (high)
XBUS accesses
Tristated (floating) for read accesses
XBUS write data for write accesses
Last used XBUS address
(if used for the bus interface)
Last used XBUS segment address
(on selected pins)
Inactive (high) for selected CS signals
Level corresponding to last XBUS
access
Pulses as defined for X-Peripheral
Inactive (high)
Inactive (high)
Inactive (high)
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