C161V_96 Datasheet, PDF (241/260 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:19h
The Register Set / C161
Name
DP3
DP4
DP6
DPP0
DPP1
DPP2
DPP3
EXICON
MDC
MDH
MDL
ODP2
ODP3
ODP6
ONES
P0L
P0H
P1L
P1H
P2
P3
P4
P5
P6
PECC0
PECC1
PECC2
PECC3
PECC4
PECC5
PECC6
PECC7
PSW
Physical 8-Bit
Description
Address Address
b FFC6_H E3_H
b FFCA_H E5_H
b FFCE_H E7_H
FE00_H 00_H
FE02_H 01_H
FE04_H 02_H
FE06_H 03_H
b F1C0_H E E0_H
b FF0E_H 87_H
FE0C_H 06_H
FE0E_H 07_H
b F1C2_H E E1_H
b F1C6_H E E3_H
b F1CE_H E E7_H
b FF1E_H 8F_H
b FF00_H 80_H
b FF02_H 81_H
b FF04_H 82_H
b FF06_H 83_H
b FFC0_H E0_H
b FFC4_H E2_H
b FFC8_H E4_H
b FFA2_H D1_H
b FFCC_H E6_H
FEC0_H 60_H
FEC2_H 61_H
FEC4_H 62_H
FEC6_H 63_H
FEC8_H 64_H
FECA_H 65_H
FECC_H 66_H
FECE_H 67_H
b FF10_H 88_H
Port 3 Direction Control Register
Port 4 Direction Control Register
Port 6 Direction Control Register
CPU Data Page Pointer 0 Register (10 bits)
CPU Data Page Pointer 1 Register (10 bits)
CPU Data Page Pointer 2 Register (10 bits)
CPU Data Page Pointer 3 Register (10 bits)
External Interrupt Control Register
CPU Multiply Divide Control Register
CPU Multiply Divide Register – High Word
CPU Multiply Divide Register – Low Word
Port 2 Open Drain Control Register
Port 3 Open Drain Control Register
Port 6 Open Drain Control Register
Constant Value 1’s Register (read only)
Port 0 Low Register (Lower half of PORT0)
Port 0 High Register (Upper half of PORT0)
Port 1 Low Register (Lower half of PORT1)
Port 1 High Register (Upper half of PORT1)
Port 2 Register
Port 3 Register
Port 4 Register (8 bits)
Port 5 Register (read only)
Port 6 Register (8 bits)
PEC Channel 0 Control Register
PEC Channel 1 Control Register
PEC Channel 2 Control Register
PEC Channel 3 Control Register
PEC Channel 4 Control Register
PEC Channel 5 Control Register
PEC Channel 6 Control Register
PEC Channel 7 Control Register
CPU Program Status Word
Semiconductor Group
17-5
Reset
Value
0000_H
00_H
00_H
0000_H
0001_H
0002_H
0003_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
00_H
FFFF_H
00_H
00_H
00_H
00_H
0000_H
0000_H
00_H
XXXX_H
00_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H