C161V_96 Datasheet, PDF (162/260 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:19h
The General Purpose Timer Units / C161
GPT2 Core Timer T6
The operation of the core timer T6 is controlled by its bitaddressable control register T6CON.
T6CON (FF48_H / A4_H)
15 14 13 12 11 10 9
T6
T6SR -
-
-
- _OTL -
rw -
-
-
- rw -
SFR
Reset Value: 0000_H
876543210
- T6UD T6R
T6M
T6I
- rw rw
rw
rw
Bit
T6I
T6M
T6R
T6UD
T6OTL
T6SR
Function
Timer 6 Input Selection
Depends on the Operating Mode, see below.
Timer 6 Mode Control (Basic Operating Mode)
000:
Timer Mode
Note:
The other combinations of T6M are reserved
and lead to undefined behaviour if selected.
Timer 6 Run Bit
T6R = ‘0’: Timer / Counter 6 stops
T6R = ‘1’: Timer / Counter 6 runs
Timer 6 Up / Down Control
Timer 6 Output Toggle Latch
Toggles on each overflow / underflow of T6. Can be set or reset by software.
Timer 6 Reload Mode Enable
T6SR = ‘0’: Reload from register CAPREL Disabled
T6SR = ‘1’: Reload from register CAPREL Enabled
Timer 6 Run Bit
The timer can be started or stopped by software through bit T6R (Timer T6 Run Bit). If T6R=‘0’, the
timer stops. Setting T6R to ‘1’ will start the timer.
Count Direction Control
The count direction of the core timer can be controlled via software by setting or clearing bit T6UD.
The count direction can be changed regardless of whether the timer is running or not.
Timer 6 Output Toggle Latch
An overflow or underflow of timer T6 will clock the toggle bit T6OTL in control register T6CON.
T6OTL can also be set or reset by software. T6OTL can be used in conjunction with the timer over/
underflows as an input for the counter function of the auxiliary timer T5.
Semiconductor Group
9-18