C161V_96 Datasheet, PDF (41/260 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:19h ^{The Central Processing Unit (CPU) / C161}
1 Machine
Cycle
FETCH
I₁
I₂
I₃
I₄
I₅
I₆
DECODE
I₁
I₂
I₃
I₄
I₅
EXECUTE
I₁
I₂
I₃
I₄
WRITEBACK
I₁
I₂
I₃
time
Figure 4-2
Sequential Instruction Pipelining
Standard Branch Instruction Processing
Instruction pipelining helps to speed sequential program processing. In the case that a branch is
taken, the instruction which has already been fetched providently is mostly not the instruction which
must be decoded next. Thus, at least one additional machine cycle is normally required to fetch the
branch target instruction. This extra machine cycle is provided by means of an injected instruction
(see figure below).
1 Machine
Cycle
FETCH BRANCH I_n+2
Injection
I_TARGET I_TARGET+1 I_TARGET+2 I_TARGET+3
DECODE
I_n
BRANCH (I_INJECT) I_TARGET I_TARGET+1 I_TARGET+2
EXECUTE
...
I_n
BRANCH (I_INJECT) I_TARGET I_TARGET+1
WRITEBACK . . .
...
I_n
BRANCH (I_INJECT) I_TARGET
time
Figure 4-3
Standard Branch Instruction Pipelining
If a conditional branch is not taken, there is no deviation from the sequential program flow, and thus
no extra time is required. In this case the instruction after the branch instruction will enter the decode
stage of the pipeline at the beginning of the next machine cycle after decode of the conditional
branch instruction.
Semiconductor Group
4-4