C161V_96 Datasheet, PDF (160/260 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:19h
The General Purpose Timer Units / C161
9.2 Timer Block GPT2
From a programmer’s point of view, the GPT2 block is represented by a set of SFRs as summarized
below. Those portions of port and direction registers which are used for alternate functions by the
GPT2 block are shaded.
Ports & Direction Control
Alternate Functions
Data Registers
Control Registers
Interrupt Control
ODP3
E
T5
DP3
T6
P3
CAPREL
CAPIN/P3.2
ODP3
DP3
P3
T5CON
T6CON
Port 3 Open Drain Control Register
Port 3 Direction Control Register
Port 3 Data Register
GPT2 Timer 5 Control Register
GPT2 Timer 6 Control Register
T5CON
T6CON
T5IC
T6IC
CRIC
T5
T6
CAPREL
T5IC
T6IC
CRIC
GPT2 Timer 5 Register
GPT2 Timer 6 Register
GPT2 Capture/Reload Register
GP_CT2_onT_tim_roe_lr_R5_eIn_gt_ie_sr_tr_eu_rp_st Control Register
GPT2 Timer 6 Interrupt Control Register
GPT2 CAPREL Interrupt Control Register
Figure 9-11
SFRs and Port Pins Associated with Timer Block GPT2
Note: GPT2 is only provided on the C161O.
Timer block GPT2 supports high precision event control with a maximum resolution of 250 ns (@
16 MHz CPU clock). It includes the two timers T5 and T6, and the 16-bit capture/reload register
CAPREL. Timer T6 is referred to as the core timer, and T5 is referred to as the auxiliary timer of
GPT2.
The count direction (Up / Down) may be programmed via software. An overflow/underflow of T6 is
indicated by the output toggle bit T6OTL. In addition, T6 may be reloaded with the contents of
CAPREL.
The toggle bit supports the concatenation of T6 with auxiliary timer T5. Triggered by an external
signal, the contents of T5 can be captured into register CAPREL, and T5 may optionally be cleared.
Both timer T6 and T5 can count up or down, and the current timer value can be read or modified by
the CPU in the non-bitaddressable SFRs T5 and T6.
Semiconductor Group
9-16