C161V_96 Datasheet, PDF (154/260 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:19h
The General Purpose Timer Units / C161
Timers T2 and T4 in Counter Mode
Counter mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective
register TxCON to ‘001_B’. In counter mode timers T2 and T4 can be clocked either by a transition
at the respective external input pin TxIN, or by a transition of timer T3’s output toggle latch T3OTL.
x = 2,4
Figure 9-6
Block Diagram of an Auxiliary Timer in Counter Mode
The event causing an increment or decrement of a timer can be a positive, a negative, or both a
positive and a negative transition at either the respective input pin, or at the toggle latch T3OTL.
Bit field TxI in the respective control register TxCON selects the triggering transition (see table
below).
GPT1 Auxiliary Timer (Counter Mode) Input Edge Selection
T2I / T4I
X00
001
010
011
101
110
111
Triggering Edge for Counter Increment / Decrement
None. Counter Tx is disabled
Positive transition (rising edge) on TxIN
Negative transition (falling edge) on TxIN
Any transition (rising or falling edge) on TxIN
Positive transition (rising edge) of output toggle latch T3OTL
Negative transition (falling edge) of output toggle latch T3OTL
Any transition (rising or falling edge) of output toggle latch T3OTL
Note: Only state transitions of T3OTL which are caused by the overflows/underflows of T3 will
trigger the counter function of T2/T4. Modifications of T3OTL via software will NOT trigger
the counter function of T2/T4.
Semiconductor Group
9-10