HYB514100BJ-50- Datasheet, PDF (8/21 Pages) Siemens Semiconductor Group – 4M x 1-Bit Dynamic RAM

HYB 514100BJ-50/-60
4M × 1 DRAM
Notes
1. All voltages are referenced to V_SS.
2. I_CC1, I_CC3, I_CC4 and I_CC6 depend on cycle rate.
3. I_CC1 and I_CC4 depend on output loading. Specified values are measured with the output open.
4. Address can be changed once or less while RAS = V_IL. In the case of I_CC4 it can be changed once
or less during a fast page mode cycle (t_PC).
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS
cycles are required.
6. AC measurements assume t_T = 5 ns.
7. V_{IH (MIN.)} and V_{IL (MAX.)} are reference levels for measuring timing of input signals. Transition times
are also measured between V_IH and V_IL.
8. Measured with a load equivalent to 2 TTL loads and 100 pF.
9. Operation within the t_{RCD (MAX.)} limit ensures that t_{RAC (MAX.)} can be met. t_{RCD (MAX.)} is specified as
a reference point only: If t_RCD is greater than the specified t_{RCD (MAX.)} limit, then access time is
controlled by t_CAC.
10.Operation within the t_{RAD (MAX.)} limit ensures that t_{RAC (MAX.)} can be met. t_{RAD (MAX.)} is specified as
a reference point only: If t_RAD is greater than the specified t_{RAD (MAX.)} limit, then access time is
controlled by t_AA.
11.Either t_RCH or t_RRH must be satisfied for a read cycle.
12.t_{OFF (MAX.)} defines the time at which the outputs achieve the open-circuit condition and are not
referenced to output voltage levels.
13.t_WCS, t_RWD, t_CWD, t_AWD and t_CPWD are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If t_WCS > t_{WCS (MIN.)}, the cycle is an early write cycle
and the data out pin will remain open-circuit (high impedance) through the entire cycle; if
t_RWD > t_{RWD (MIN.)}, t_CWD > t_{CWD (MIN.)}, t_AWD > t_AWD(MIN.) and t_CPWD > t_{CPWD (MIN.)}, the cycle is a read-
write cycle and DO will contain data read from the selected cells. If neither of the above sets of
conditions is satisfied, the condition of the DO pin (at access time) is indeterminate.
14.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
Semiconductor Group
8
1998-10-01