HYB514100BJ-50- Datasheet, PDF (6/21 Pages) Siemens Semiconductor Group – 4M x 1-Bit Dynamic RAM

HYB 514100BJ-50/-60
4M × 1 DRAM
AC Characteristics (cont’d) ^{5, 6}
T_A = 0 to 70 °C, V_CC = 5 V ± 10 %, t_T = 5 ns
Parameter
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
Symbol
Limit Values
Unit Note
-50
-60
min. max. min. max.
t_CRP
5–
5
–
ns
t_T
3
50 3
50 ns ⁷
t_REF
– 16 – 16 ms
Read Cycle
Access time from RAS
t_RAC
Access time from CAS
t_CAC
Access time from column address
t_AA
Column addr. to RAS lead time
t_RAL
Read command setup time
t_RCS
Read command hold time
t_RCH
Read command hold time referenced to RAS t_RRH
CAS to output in low–Z
t_CLZ
Output buffer turn-off delay
t_OFF
– 50
– 13
– 25
25 –
0–
0–
0–
0–
0 13
– 60
– 15
– 30
30 –
0–
0–
0–
0–
0 15
ns ^{8, 9}
ns ^{8, 9}
ns ^{8, 10}
ns
ns
ns ¹¹
ns ¹¹
ns ⁸
ns ¹²
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
Data hold time
t_WCH
t_WP
t_WCS
t_RWL
t_CWL
t_DS
t_DH
8–
8–
0–
13 –
13 –
0–
10 –
10 –
10 –
0–
15 –
15 –
0–
10 –
ns
ns
ns ¹³
ns
ns
ns ¹⁴
ns ¹⁴
Read-Modify-Write Cycle
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
t_RWC
t_RWD
t_CWD
t_AWD
115 –
50 –
13 –
25 –
130 –
60 –
15 –
30 –
ns
ns ¹³
ns ¹³
ns ¹³
Semiconductor Group
6
1998-10-01