SDA9257 Datasheet, PDF (7/36 Pages) Siemens Semiconductor Group – Clock Sync Generator

SDA 9257
Selection of Clock for Chip Operation
A line locked clock is generated by the internal PLL
Clock source is CLE. The radio between the horizontal
frequency in CVBS and CLK1 depends on control bits HPLL0
and HPLL1*
Control Bit SCLE
0
Clock Out Disable
CKL1 and CKL2 tristate
CKL1 and CKL2 enabled
Selection of Function on SC and SINC
SC-Pin Function
SINC-Pin Function
Tristate
Tristate
Super sandcastle
Sandcastle
without
burst
key
Burst key inverted
Composite sync
Serial increment and
status bits
Control Bit CLKDI
1
0
Control Bits
SSC1
SSC0
0
0
0
1
1
1
1
0
Level on I1
Low
High
Control Bit I1
0
1
Mode of Vertical Pulse Generation
No flywheel mode
Flywheel mode
Control Bit SCHW
0
1
* Pin CLE should most definitely be connected to ground in this instance in order to minimize output signal jitter
Semiconductor Group
188