SDA9257 Datasheet, PDF (10/36 Pages) Siemens Semiconductor Group – Clock Sync Generator

SDA 9257
Center Frequency
(of VCO)
Approx. 22.4 MHz
Approx. 24.0 MHz
Approx. 25.6 MHz
Approx. 27.0 MHz
Approx. 29.0 MHz
Approx. 31.0 MHz
Approx. 33.0 MHz
Approx. 35.0 MHz
VCO2
0
0
0
0
1
1
1
1
Control Bits
VCO1
1
1
0
0
1
1
0
0
Note: The pull-in range of the VCO is ± 8 %, irrespective of the center frequency
VCO0
1
0
1
0
1
0
1
0
External Clock Frequency Setting (subaddresses 03 and 04)
Clock Frequency on CLK1 (FQ = XTAL Frequency,
[INC] = Digital Value of INC15 … INC00)
EXINC bit must be set)
(MSB)
INC15
F = FQ × 4 • 65536/262144 = FQ
0
F = FQ × 4 • (65536 + [INC])/262144
F = FQ × 4 • (65536 + 65535)/262144 = 2 x FQ
1
Control Bits
(binary offset)
INC14 …
0
…
...
1
…
(LSB)
INC00
0
1
Note: When clock frequencies below 24 MHz or above 29 MHz are selected, the VCO should be
set with control bits VCO2 … VCO0 as well. Clock jitter may rise when crystal clock FQ is
changed.
Semiconductor Group
191