SDA9257 Datasheet, PDF (2/36 Pages) Siemens Semiconductor Group – Clock Sync Generator

SDA 9257
Circuit Description
1 Horizontal PLL (HPLL)
The CVBS is clamped before A/D conversion such that the H-sync pulse level is applied to the
analog ground. Conversion takes place with 7 bits and a nominal frequency of 27 MHz. The digital
HPLL filters the signal with a cutoff frequency of 1 MHz for a decimated clock frequency of
13.5 MHz, then measures the black level, calculates the sync threshold and determines the phase
difference between the horizontal pulse and its own phase position. By means of digital PI filtering
an increment is gained from this for the Discrete Timing Oscillator (DTO). The PI filter can be set by
the bus so that the lock-in behavior of the PLL is optimal in relation to either the TV or VCR mode.
The DTO generates a saw-tooth with a frequency that is proportional to the increment, i.e. one
quarter of the clock frequency on pin CLK1 (nominally 27 MHz). The saw-tooth is converted into a
sinusoidal clock signal by means of sin ROMs and D/A converters and applied to an analog PLL
which quadruples the frequency and minimizes residual jitter. In this manner a clock is provided that
is line-locked with the CVBS-input signal. The ratio of this clock frequency to the horizontal
frequency of CVBS can be set to the values 1728, 1716 or 1536 by the I²C Bus.
The digital horizontal PLL supplies a further composite sync signal derived directly from the CVBS,
a noise-suppressed horizontal pulse and a non-suppressed vertical pulse obtained by digital
integration of the main equalizing pulses. An integration time of 26.6 µs or 11.3 µs can be set by the
I²C Bus. The HPLL is driven in the “external clock mode” by the 24-MHz clock supplied by pin CKE
and locks onto CVBS by continually locking the relationship between the input clock and the
horizontal frequency of CVBS (768 ± 32).
The HPLL can lock onto a composite sync signal using application circuit 5. The edges on pin
CVBS should not be steeper than 100 ns.
2 Vertical Sync Processing
Vertical sync processing consists of:
q 625/525 line detection
q Vertical noise suppression
The 625/525 line detector measures the range of lines within a field into which the vertical pulses
will fall that were obtained from the CVBS signal by integration. By taking the average of the
individual measurements with two up/down counters, the status bits “FF” and “FFGF” (refer to
timing diagram 8 and I²C Bus) are obtained.
When vertical noise suppression is switched on (V_OFF = 0), the vertical pulse obtained from the
CVBS signal by integration is admitted only within a preset window (refer to timing diagram 8) and
appears as a VS pulse. The width of the window can be set with the I²C Bus bit VWW.
In the temporary absence of vertical pulses in CVBS, a continuous VS can be generated by
switching on a “flywheel mode” (SCHW = 1) provided that the number of lines per field in CVBS is
312.5 or 262.5 respectively.
Semiconductor Group
183