SDA9257 Datasheet, PDF (22/36 Pages) Siemens Semiconductor Group – Clock Sync Generator

SDA 9257
Characteristics (cont’d)
T_A = 25 °C (all voltages are referred to V_SS)
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
CLK1, CLK2 Outputs
L-output voltage
H-output voltage
Load capacitance
Transition times
Low time
High time
Low time
High time
Skew
Jitter (rms)
V_QL
V_QH
C_L
t_R, t_F
t_WL13
t_WH13
t_WL27
t_WH27
t_SK
t_j
Frequency range
f
when PLL is locked at
CVBS
0
0.4
V
2.4
V_DD
V
50
pF
5
ns
26
ns
26
ns
10
ns
10
ns
0
4
ns
3
ns
25.72 27.00 28.26 MHz
I = 1.6 mA
I = – 0.5 mA
C_L = 30 pF
13.5 MHz ± 8 %
13.5 MHz ± 8 %
27 MHz ± 8 %
27 MHz ± 8 %
TV-time constant, 0.6 V
nominal sync amplitude
SINC Output
L-output voltage
H-output voltage
Load capacitance
Transition times
V_QL
V_QH
C_L
t_R, t_F
SC Output
H-output voltage
Vertical level output
voltage
L-output voltage
Load capacitance
Transition times
Transition times
Output delay time
Output hold time
V_QH
V_QV
V_QL
C_L
t_R, t_F
t_R, t_F
t_QD
t_QH
0
0.4
V
I = 1.6 mA
2.4
V_DD
V
I = – 0.5 mA
50
pF
5
ns
C_L = 30 pF
4.4
4.9
V
I = – 0.5 mA
2.1
2.5
2.6
V
for SSC
I = – 0.3 mA
0.4
0.8
V
I = 1.6 mA
30
pF
5
ns
for composite sync
100 ns
for SC or SSC
25
ns
for composite sync
6
ns
for composite sync
Semiconductor Group
203