SDA9257 Datasheet, PDF (6/36 Pages) Siemens Semiconductor Group – Clock Sync Generator

SDA 9257
Synoptical Table of Data Byte Formats
Receiver
Register
SUB-
ADDR. _(MSB)
Data Bits
(LSB)
Pin Control
00
OEFB SCL2 SCLE CLKDI SSC1 SSC0 I1
SCHW
HPLL Control
01
HPLL1 HPLL0 RSTH VTHRE CLOF VCRT FRZIN EXINC
V Process. - and 02
VCO Control
03
FREE VOFF VF
VWW TERM VCO2 VCO1 VCO0
INC07 INC06 INC05 INC04 INC03 INC02 INC01 INC00
External Clock- 04
Frequency Control
INC15 INC14 INC13 INC12 INC11 INC10 INC09 INC08
BLN Start Time 05
BON8 BON7 BON6 BON5 BON4 BON3 BON2 BON1
BLN Stop Time 06
BOF8 BOF7 BOF6 BOF5 BOF4 BOF3 BOF2 BOF1
H1 Start Time
07
H10N8 H10N7 H10N6 H10N5 H10N4 H10N3 H10N2 H10N1
H1 Stop Time
08
H10F8 H10F7 H10F6 H10F5 H10F4 H10F3 H10F2 H10F1
H2 Start Time
09
H20N8 H20N7 H20N6 H20N5 H20N4 H20N3 H20N2 H20N1
H2 Stop Time
10
H20F8 H20F7 H20F6 H20F5 H20F4 H20F3 H20F2 H20F1
HS Start Time
11
HS0N8 HS0N7 HS0N6 HS0N5 HS0N4 HS0N3 HS0N2 HS0N1
SC Start Time
12
SC0N8 SC0N7 SC0N6 SC0N5 SC0N4 SC0N3 SC0N2 SC0N1
FRZINC TIME
13
FI0N4 FI0N3 FI0N2 FI0N1 FILE4 FILE3 FILE2 FILE1
(Automatic incrementing of the subaddress)
When operating voltage is applied (POR), all registers are set to 0.
Pin Control (subaddress 00)
Output Enable by Featurebox Signals
BLN, HS, VS outputs tristate
BLN, HS, VS outputs enabled
Selection of Clock Frequency on CLK2
13.5 MHz (nominal)
27 MHz (nominal)
Control Bit OEFB
0
1
Control Bit SCL2
0
1
Semiconductor Group
187