SAB88C166 Datasheet, PDF (39/58 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers with/without oscillator prescaler with 32 KByte Flash EPROM

SAB 88C166(W)
AC Characteristics (cont’d)
Multiplexed Bus for the SAB 88C166W
V_CC = 5 V ± 10 %; V_SS = 0 V
T_A = 0 to + 70 ˚C for SAB 88C166W-M
C_L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
ALE cycle time = 6 TCL + 2t_A + t_C + t_F (150 ns at 20-MHz CPU clock without waitstates)
Parameter
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
WR (with RW-delay)
Address float after RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
RD WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
RD to valid data in
(no RW-delay)
ALE low to valid data in
Address to valid data in
Data hold after RD
rising edge
Data float after RD
Symbol CPU Clock = 16 MHz
Duty cycle 0.4 to 0.6
Variable CPU Clock
1/CLP = 1 to 20 MHz
min.
max.
min.
max.
t₅CC
t₆CC
t₇CC
t₈CC
t₉CC
15 + t_A
–
10 + t_A
–
15 + t_A
–
15 + t_A
–
– 10 + t_A –
TCL_min – 10 –
+ t_A
TCL_min – 15 –
+ t_A
TCL_min – 10 –
+ t_A
TCL_min – 10 –
+ t_A
– 10 + t_A
–
Unit
ns
ns
ns
ns
ns
t₁₀CC _–
5
–
5
ns
t₁₁CC _–
42.5
–
TCL_max + 5 ns
t₁₂CC
t₁₃CC
t₁₄SR
t₁₅SR
t₁₆SR
t₁₇SR
t₁₈SR
52.5 + t_C
77.5 + t_C
–
–
–
–
0
–
–
47.5 + t_C
72.5 + t_C
72.5
+ t_A + t_C
100
+ 2t_A + t_C
–
CLP – 10 –
ns
+ t_C
CLP+TCL_min –
ns
– 10 + t_C
–
CLP – 20 ns
+ t_C
–
CLP+TCL_min ns
– 20 + t_C
–
CLP+TCL_min ns
– 20 + t_C
–
2CLP – 25 ns
+ 2t_A + t_C
0
–
ns
t₁₉SR –
47.5 + t_F –
CLP – 15 ns
+ t_F
Semiconductor Group
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