SAB88C166 Datasheet, PDF (12/58 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers with/without oscillator prescaler with 32 KByte Flash EPROM

SAB 88C166(W)
The selection of Flash Operation and Read Mode is done via the three bits FWE, FEE and
FWMSET. The table below shows the combinations for these bits to select a specific function:
FWMSET FEE
1
1
1
0
1
X
0
X
FWE
1
1
0
X
Flash Operation Mode
Erasing mode
Programming mode
Non-Verify mode
Standard mode
Flash Read Mode
Erase-Verify-Read via [Rn]
Program-Verify-Read via [Rn]
Normal Read via [Rn]
Normal Read via [Rn] or mem
FWE enables/disables write operations, FEE selects erasing or programming, FWMSET controls
the writing mode. Bits FWE and FEE select an operation, but do not execute it directly.
Note: Watch the FWMSET bit, when writing to register FCR (word access only), in order not to exit
Flash writing mode unintentionally by clearing bit FWMSET.
FBUSY: This read-only flag is set to ‘1’ while a Flash programming or erasing operation is in
progress. FBUSY is set via hardware, when the respective command is issued.
RPROT: This write-only Flash Read Protection bit determines whether Flash protection is active
or inactive. RPROT is the only FCR bit which can be modified even in the Flash standard mode but
only by an instruction executed from the on-chip Flash memory itself. Per reset, RPROT is set to ‘1’.
Note: RPROT is only significant, if the general Flash memory protection is enabled.
FCVPP and VPPREV: These read-only bits allow to monitor the V_PP voltage. The Flash Vpp
Revelation bit VPPREV reflects the state of the V_PP voltage in the Flash writing mode (VPPREV =
‘0’ indicates that V_PP is below the threshold value necessary for reliable programming or erasure,
otherwise VPPREV = ‘1’). The Flash Control V_PP bit FCVPP indicates, if V_PP fell below the valid
threshold value during a Flash programming or erase operation (FCVPP = ‘1’). FCVPP = ‘0’ after
such an operation indicates that no critical discontinuity on V_PP has occurred.
CKCTL: This Flash Timer Clock Control bitfield controls the width of the programming or erase
pulses (TPRG) applied to Flash memory cells during the corresponding operation. The width of a
single programming or erase pulse and the cumulated programming or erase time must not exceed
certain values to avoid putting the Flash memory under critical stress (see table below).
Time Specification
Maximum Programming Pulse Width
Maximum Cumulated Programming Time
Maximum Erase Pulse Width
Maximum Cumulated Erase Time
Limit Value
128 µs
2.5
ms
10
ms
30
s
Semiconductor Group
11