SAB88C166 Datasheet, PDF (26/58 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers with/without oscillator prescaler with 32 KByte Flash EPROM

SAB 88C166(W)
WAIT_ERASE:
MOV R15, DPP1: pof FCR
JB
R15.2, WAIT_ERASE
…
; Polling Loop to check bit FBUSY
; Read FCR contents using 16-bit access
; Loop while bit FBUSY (FCR.2) is ‘1’
; Continue in EVM mode, when FBUSY is ‘0’
q Verify V_PP validity during erasing to make sure V_PP did not exceed its valid margins during the
erase operation. Otherwise erasing may have not been performed properly. The FCVPP flag is
set to ‘1’ in case of this error condition. If FCVPP reads ‘1’, the erase routine can abort, when V_PP
still fails, or repeat the erase operation, when V_PP proves to be stable now.
q Perform Erase-Verify operation and compare with ‘FFFF_H’ in order to check whether an
erase operation was performed correctly. EVM reading consists of two identical Flash read
instructions with 4 µs delay in between. This example uses CMP instructions to access the Flash
memory. In case of a mismatch the erase routine repeats the erase cycle provided that the
maximum number of attempts was not yet reached.
MOV
CMP
CALL
CMP
JMP
...
R15, ONES
R15, [FLASH_PTR]
cc_UC, WAIT_4
R15, [FLASH_PTR]
cc_NZ, ERASE_FAILED
; Load auxiliary GPR with anticipated value
; 1st step of EVM read
; Delay for 4 µs
; 2nd step of EVM read
; Re-erase on mismatch, if (PCOUNT) > 0
; Erasing was OK. Go on with next step.
q Check number of erase attempts to decide, if another erase attempt is allowed. PCOUNT is
decremented by ‘1’ upon each unsuccessful erase attempt. If it expires, the failing Flash memory
bank is classified as unerasable. This failure is very unlikely to occur. However, it should be
checked for safe erasing.
Note: This step is taken only in case of a erase verify mismatch.
q Check for last word and increment pointers to decide, if another cell must be verified. The
target pointer (FLASH_PTR) is incremented to the next word to be verified and checked against
the upper limit of the respective bank. If the target pointer exceeds the bank limit, the erase
routine is exited successfully.
q Disable erase operations and exit routine, when the Flash memory bank was erased
successfully or when a failure occurred. In either case bit FWE of the FCR is reset to ‘0’ and the
erase routine is exited. This means that the Flash non-verify mode is entered again, where the
FCR stays accessible but Flash memory locations can be read normally again using indirect
addressing. For returning to the Flash standard mode, bit FWMSET of the FCR must be reset to
‘0’ by the calling routine. The erase routine may return an exit code that indicates correct erasing
or identifies the type of error.
Semiconductor Group
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