SAB88C166 Datasheet, PDF (15/58 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers with/without oscillator prescaler with 32 KByte Flash EPROM

SAB 88C166(W)
After entering writing mode the first erase or programming operation must not be started for at least
10 µs. This absolute (!) delay time is required to set up the internal high voltage. In general, Flash
write operations need a 12 V external V_PP voltage to be applied to the V_PP/EBC1 pin.
It is not possible to erase or to program the Flash memory via code executed from the Flash memory
itself. The respective code must reside within the on-chip RAM or within external memory.
When programming or erasing ‘on-line’ in the target system, some considerations have to be taken:
While these operations are in progress, the Flash memory cannot be accessed as usual. Therefore
care must be taken that no branch is taken into the Flash memory and that no data reads are
attempted from the Flash memory during programming or erasure. If the Flash memory is mapped
to segment 0, it must especially be ensured that no interrupt or hardware trap can occur, because
this would implicitly mean such a ‘forbidden’ branch to the Flash memory in this case.
The UNLOCK sequence is a specific key code sequence, which is required to enable the writing
modes of the SAB 88C166(W). The UNLOCK sequence must use identical values (see example
below) and must not be interrupted:
MOV
MOV
CALL
FCR, Rw_n
[Rw_n], Rw_n
cc_UC, WAIT_10
; Dummy write to the FCR
; Both operands use the same GPR
; Delay for 10 µs (may be realized also by
; instructions other than a delay loop
where Rw_n can be any word GPR (R0…R15). [Rw_n] and FCR must point to even addresses within
the active address space of the Flash memory.
Note: Data paging and Flash segment mapping, if active, must be considered in this context.
In Flash Erase Mode (FEE=’1’, FWE=’1’) the SAB 88C166(W) is prepared to erase the bank
selected by the Bank Erase (BE) bit field in the FCR. The width of the erase pulses generated
internally is defined by the Internal Flash Timer Clock Control (CKCTL) bit field of the FCR. The
maximum number of erase pulses (EN_max) applied to the Flash memory is determined by software
in the Flash erase algorithm. The chosen values for CKCTL and EN_max must guarantee a maximum
cumulated erase time of 30 s per bank and a maximum erase pulse width of 20 ms.
The Flash bank erase operation will not start before the erase command is given. This provides
additional security for the erase operation. The erase command can be any write operation to a
Flash location, where the data and the even address written to must be identical:
MOV [Rw_n], Rw_n
; Both operands use the same GPR
Upon the execution of this instruction, the Flash Busy (FBUSY) flag is automatically set to ‘1’
indicating the start of the operation. End of erasure can be detected by polling the FBUSY flag. V_PP
must stay within the valid margins during the entire erase process.
At the end of erasure the Erase-Verify-Mode (EVM) is entered automatically. This mode allows to
check the effect of the erase operation (see description below).
Note: Before the erase algorithm can be properly executed, the respective bank of the Flash
memory must be programmed to all zeros (‘0000_H’).
Semiconductor Group
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