SAB88C166 Datasheet, PDF (33/58 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers with/without oscillator prescaler with 32 KByte Flash EPROM

SAB 88C166(W)
A/D Converter Characteristics
V_CC = 5 V ± 10 %; V_SS = 0 V
T_A = 0 to + 70 ˚C for SAB 88C166(W)-5M
4.0 V ≤ V_AREF ≤ V_CC + 0.1 V; V_SS – 0.1 V ≤ V_AGND ≤ V_SS + 0.2 V
Parameter
Analog input voltage range
Sample time
Conversion time
Total unadjusted error
Internal resistance of reference
voltage source
Internal resistance of analog
source
ADC input capacitance
Symbol
Limit Values Unit
min.
max.
V_AINSR
t_SCC
t_CCC
V_AGND
–
–
TUECC –
V_AREF
V
2 t_SC
10 t_CC +
t_S + 4TCL
±2
LSB
R_AREFCC –
t_CC / 250 kΩ
- 0.25
R_ASRCCC –
t_S / 500 kΩ
– 0.25
C_AINCC –
50
pF
Test Condition
1)
2) 4)
3) 4)
5)
t_CC in [ns] ^{6) 7)}
t_S in [ns] ^{2) 7)}
7)
Notes
1) _{VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these}
cases will be X000_H or X3FF_H, respectively.
2) _{During the sample time the input capacitance CI can be charged/discharged by the external source. The}
internal resistance of the analog source must allow the capacitors to reach their final voltage level within t_S.
After the end of the sample time t_S, changes of the analog input voltage have no effect on the conversion result.
The value for the sample clock is t_SC = TCL x 32.
3) _{This parameter includes the sample time tS, the time for determining the digital result and the time to load the}
result register with the conversion result.
The value for the conversion clock is t_CC = TCL x 32.
4) _{This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.}
5) _{TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.8 V. It is guaranteed by design characterization for all}
other voltages within the defined voltage range.
6) _{During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal}
resistance of the reference voltage source must allow the capacitors to reach their respective voltage level
within t_CC. The maximum internal resistance results from the CPU clock period.
7) _{Not 100% tested, guaranteed by design characterization.}
Semiconductor Group
32