SAB88C166 Datasheet, PDF (13/58 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers with/without oscillator prescaler with 32 KByte Flash EPROM

SAB 88C166(W)
In order not to exceed the limit values listed above, a specific CKCTL setting requires a minimum
CPU clock frequency, as listed below.
Setting of
CKCTL
00
01
10
11
Length of
TPRG
2⁷ * 1/f_CPU
2¹¹ * 1/f_CPU
2¹⁵ * 1/f_CPU
2¹⁸ * 1/f_CPU
TPRG
@ f_CPU = 20 MHz
6.4 µs
f_CPUmin
for programming
1 MHz
102.4 µs
16 MHz
1.64 ms
---
13.11 ms
---
f_CPUmin
for erasing
---
1 MHz
3.28 MHz
13.11 MHz
The maximum number of allowed programming or erase attempts depends on the CPU clock
frequency and on the CKCTL setting chosen in turn. This number results from the actual pulse width
compared to the maximum pulse width (see above tables).
The table below lists some sample frequencies, the respective recommended CKCTL setting and
the resulting maximum number of program / erase pulses:
f_CPU
1 MHz
10 MHz
16 MHz
20 MHz
CKCTL
00
00
00
00
Programming
TPROG
128 µs
N_PROGmax
19
12.8 µs
195
8 µs
312
6.4 µs
390
CKCTL
01
10
10
10
Erasing
TPROG
2.05 ms
3.28 ms
2.05 ms
1.64 ms
N_ERASEmax
14648
9155
14648
18310
BE: The Flash Bank Erasing bit field determines the Flash memory bank to be erased (see table
below). The physical addresses of the selected bank depend on the Flash memory mapping
chosen.
BE setting
00
01
10
11
Bank
0
1
2
3
Addresses Selected for Erasure (x = 0 or 1)
x’0000_H to x’2FFF_H
x’3000_H to x’5FFF_H
x’6000_H to x’77FF_H
x’7800_H to x’7FFF_H
Semiconductor Group
12