HYB514265BJ-400 Datasheet, PDF (14/28 Pages) Siemens Semiconductor Group – 256K x 16-Bit EDO-Dynamic RAM

HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
7) V_{IH (min.)} and V_{IL (max.)} are reference levels for measuring timing of input signals. Transition times are also
measured between V_IH and V_IL.
8) Measured with the specified current load and 50 pF at V_OL = 0.8 V and V_OH = 2.0 V. Access time is determined
by the latter of t_RAC, t_CAC, t_AA, t_CPA , t_OEA. t_CAC is measured from tristate
.
+ 1.5 V
50 Ohm
Z=50 Ohm
I/O
50 pF
fig.2
9) Operation within the t_{RCD (max.)} limit ensures that t_{RAC (max.)} can be met. t_{RCD (max.)} is specified as a reference point
only. If t_RCD is greater than the specified t_{RCD (max.)} limit, then access time is controlled by t_CAC.
10) Operation within the t_{RAD (max.)} limit ensures that t_{RAC (max.)} can be met. t_{RAD (max.)} is specified as a reference point
only. If t_RAD is greater than the specified t_{RAD (max.)} limit, then access time is controlled by t_AA.
11) Either t_RCH or t_RRH must be satisfied for a read cycle.
t 12) , _{OFF (max.)} t_{OEZ (max.)} define the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels. t_OFF is referenced from the rising edge of RAS or CAS, whichever occurs
last.
13) Either t_DZC or t_DZO must be satisfied.
14) Either t_CDD or t_ODD must be satisfied.
15) t_WCS, t_RWD, t_CWD and t_AWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If t_WCS > t_{WCS (min.)}, the cycle is an early write cycle and data out pin will remain
open-circuit (high impedance) through the entire cycle; if t_RWD > t_{RWD (min.)}, t_CWD > t_{CWD (min.)} and t_AWD > t_{AWD (min.)},
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh.
Semiconductor Group
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