HYB514265BJ-400 Datasheet, PDF (13/28 Pages) Siemens Semiconductor Group – 256K x 16-Bit EDO-Dynamic RAM

HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
AC Characteristics (cont’d) ⁵⁾⁶⁾
T_A = 0 to 70 ˚C, t_T = 2 ns
Parameter
16E
Symbol
Limit Values
Unit Note
-45
-50
min. max. min. max.
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) read-write cycle time t_PRWC 51 –
CAS precharge to WE
t_CPWD 41
–
CAS-before-RAS Refresh Cycle
CAS setup time
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
t_CSR
5
–
t_CHR
10
–
t_RPC
5
–
t_WRP
10
–
t_WRH
10
–
CAS-before-RAS Counter Test Cycle
CAS precharge time
t_CPT
30 –
Self Refresh Cycle (L-version)
RAS pulse width
RAS precharge
CAS hold time
t_RASS
t_RPS
t_CHS
100k –
110 –
– 50 –
58 –
41 –
10 –
10 –
5
–
10 –
10 –
35 –
100k –
95 –
– 50 –
ns
ns
ns
ns
ns
ns
ns
ns
ns 17
ns 17
ns 17
Notes:
1) All voltages are referenced to V_SS.
2) I_CC1, I_CC3, I_CC4 and I_CC6 depend on cycle rate.
3) I_CC1 and I_CC4 depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = V_IL. In case of I_CC4 it can be changed once or less during
a hyper page mode (EDO) cycle
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume t_T = 2 ns.
Semiconductor Group
13