DS_K7R323682M Datasheet, PDF (9/19 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM

K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR^TM II b2 SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
K
R
Stopped
X
D
W
D(A0)
D(A1)
Q(A0)
Q
Q(A1)
X
Previous state
Previous state
Previous state
Previous state
↑
H
H
X
X
High-Z
High-Z
↑
L
X
X
X
DOUT at C(t+1)
DOUT at C(t+2)
↑
X
L
Din at K(t)
Din at K(t)
X
X
Notes: 1. X means "Don ′t Care".
2. The rising edge of clock is symbolized by ( ↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
OPERATION
Clock Stop
No Operation
Read
Write
WRITE TRUTH TABLE(x18)
K
K
B W0
BW1
OPERATION
↑
L
L
WRITE ALL BYTEs ( K↑ )
↑
L
L
↑
L
H
WRITE ALL BYTEs ( K↑ )
WRITE BYTE 0 ( K↑ )
↑
L
H
↑
H
L
↑
H
L
WRITE BYTE 0 ( K↑ )
WRITE BYTE 1 ( K↑ )
WRITE BYTE 1 ( K↑ )
↑
H
H
↑
H
H
WRITE NOTHING ( K↑ )
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices. x9 device operation is similar except that BW controls D0:D8.
WRITE TRUTH TABLE(x36)
K
K
B W0
BW 1
B W2
BW 3
OPERATION
↑
L
L
L
L
WRITE ALL BYTEs ( K ↑ )
↑
L
L
L
L
↑
L
H
H
H
WRITE ALL BYTEs ( K↑ )
WRITE BYTE 0 ( K ↑ )
↑
L
H
H
H
↑
H
L
H
H
WRITE BYTE 0 ( K↑ )
WRITE BYTE 1 ( K ↑ )
↑
H
L
H
H
↑
H
H
L
L
↑
H
H
L
L
WRITE BYTE 1 ( K↑ )
WRITE BYTE 2 and BYTE 3 ( K↑ )
WRITE BYTE 2 and BYTE 3 ( K↑ )
↑
H
H
H
H
↑
H
H
H
H
WRITE NOTHING ( K↑ )
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
-9-
Dec. 2003
Rev 2.0