DS_K7R323682M Datasheet, PDF (16/19 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM

K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR^TM II b2 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
A,D
K,K
C,C
Q
CQ
CQ
TDI
TMS
TCK
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
TDO
JTAG Instruction Coding
IR2 IR1 IR0 Instruction
0 0 0 EXTEST
0 0 1 IDCODE
0 1 0 SAMPLE-Z
0 1 1 RESERVED
1 0 0 SAMPLE
1 0 1 RESERVED
1 1 0 RESERVED
1 1 1 BYPASS
TDO Output
Boundary Scan Register
Identification Register
Boundary Scan Register
Do Not Use
Boundary Scan Register
Do Not Use
Do Not Use
Bypass Register
Notes
1
3
2
6
5
6
6
4
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to V SS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
TAP Controller State Diagram
1 Test Logic Reset
0
1
0
Run Test Idle
1
1
1
Select DR
0
Capture DR
0
Shift DR
1
Exit1 DR
0
Pause DR
1
Exit2 DR
1
Update DR
0
1
1
0
1
0
0
1
Select IR
0
Capture IR
0
Shift IR
0
1
Exit1 IR
0
Pause IR
0
1
0
Exit2 IR
1
0
Update IR
1
- 16 -
Dec. 2003
Rev 2.0