DS_K7R323682M Datasheet, PDF (5/19 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM

K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR^TM II b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7R320982M(4Mx9)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS / S A *
SA
W
NC
K
NC
R
SA
SA
CQ
B
NC
NC
NC
SA
NC
K
BW
SA
NC
NC
Q3
C
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
D3
D
NC
D4
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
V DDQ
NC
D2
Q2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
V DDQ
NC
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
V DDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
V DDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
V DDQ
NC
Q1
D1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
V DDQ
NC
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
V DDQ
NC
NC
Q0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D0
N
NC
D7
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
Q7
SA
SA
C
SA
SA
NC
D8
Q8
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Notes: 1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 2A for 72Mb.
2. BW controls write to D0:D8 .
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-8
Q0-8
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
11M,11J,10E,11C,2D,2G,3L,2N,10P
11L,10J,11E,11B,3E,3G,2L,3P,11P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
Data Outputs
NOTE
1
W
R
BW
VREF
ZQ
VDD
VDDQ
V SS
TMS
TDI
TCK
TDO
NC
4A
Write Control Pin,active when low
8A
Read Control Pin,active when low
7B
Nybble Write Control Pin,active when low
2H,10H
Input Reference Voltage
11H
Output Driver Impedance Control Input 2
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
10R
JTAG Test Mode Select
11R
JTAG Test Data Input
2R
JTAG Test Clock
1R
JTAG Test Data Output
7A,5A,1B,2B,3B,5B,9B,10B,1C,2C,3C,9C,10C,1D,3D,9D,10D,11D
1E,2E,9E,1F,2F,3F,9F,10F,11F,1G,9G,10G,11G,1J,2J,3J,9J
1K,2K,3K,10K,11K,9K,1L,9L,10L,1M,2M,3M,9M,10M,1N,3N,9N
No Connect
3
10N,11N,1P,2P,9P
Notes: 1. C, C, K or K cannot be set to V R E F voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-5-
Dec. 2003
Rev 2.0