DS_K7R323682M Datasheet, PDF (10/19 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM

K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR^TM II b2 SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Voltage on VDD Supply Relative to VSS
VDD
-0.5 to 2.9
V
Voltage on VDDQ Supply Relative to VSS
VDDQ
-0.5 to V DD
V
Voltage on Input Pin Relative to VSS
VIN
-0.5 to VDD+0.3
V
Storage Temperature
TSTG
-65 to 150
°C
Operating Temperature
T OPR
0 to 70
°C
Storage Temperature Range Under Bias
TBIAS
-10 to 85
°C
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operati ng sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
DC ELECTRICAL CHARACTERISTICS(VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT NOTES
Input Leakage Current
IIL
VDD=Max ; VIN=V SS to VDDQ
-2
+2
µA
Output Leakage Current
IOL Output Disabled,
-2
+2
µA
Operating Current (x36): DDR
VDD=Max , IOUT=0mA
ICC
Cycle Time ≥ tKHKH Min
-20
-
-16
-
870
mA 1,5
740
Operating Current (x18): DDR
VDD=Max , IOUT=0mA
ICC
Cycle Time ≥ tKHKH Min
-20
-
-16
-
760
mA 1,5
650
Operating Current ( x9): DDR
VDD=Max , IOUT=0mA
ICC
Cycle Time ≥ tKHKH Min
-20
-
-16
-
720
mA 1,5
620
Standby Current(NOP): DDR
Device deselected, I OUT=0mA, -20
-
ISB1 f=Max,
All Inputs ≤0.2V or ≥ V DD-0.2V ^-16
-
300
mA 1,6
270
Output High Voltage
VOH1
VDDQ/2-0.12 VDDQ/2+0.12 V
2,7
Output Low Voltage
VOL1
VDDQ/2-0.12 VDDQ/2+0.12 V
3,7
Output High Voltage
VOH2 IOH=-1.0mA
VDDQ-0.2
VDDQ
V
4
Output Low Voltage
VOL2 IOL=1.0mA
VSS
0.2
V
4
Input Low Voltage
VIL
-0.3
VREF-0.1
V
8,9
Input High Voltage
VIH
VREF+0.1
VDDQ +0.3
V
8,10
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5) ±15% for 175 Ω ≤ RQ ≤ 350Ω .
3. |IOL|=(VDDQ/2)/(RQ/5) ±15% for 175Ω ≤ RQ ≤ 350Ω.
4. Minimum Impedance Mode when ZQ pin is connected to VDDQ .
5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst opeactions are completed.
7. Programmable Impedance Mode.
8. These are DC test criteria. DC design criteria is V REF±50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.
9. V IL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).
10. VIH (Max)DC= VDDQ+0.3, V IH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).
- 10 -
Dec. 2003
Rev 2.0