DS_K7R323682M Datasheet, PDF (14/19 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM

K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR^TM II b2 SRAM
TIMING WAVE FORMS OF READ AND NOP
READ
READ
NOP
tK H K H
tKLKH
K
tK H K L
tK HKH
K
READ
tAVKH tKHAX
NOP
SA
A1
A2
tIVKH tKHIX
R
Q(Data Out)
C
C
tKHKH
tK L K H
tKHKL
CQ
A3
tCHQX 1
tKHCH
Q1-1 Q1-2
tCHQV
tCHQX
Q2-1
Q2-2
tCHQZ
tKH K H
tCHQV
tC QHQV
tC H C Q V
t CQ H Q X
tCHCQV
tC H C Q X
CQ
tCHCQX
Q3-1
Don′t Care Undefined
Note : 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
2. Outputs are disabled one cycle after a NOP.
TIMING WAVE FORMS OF WRITE AND NOP
WRITE
WRITE NOP
tKHKH
tKLKH
K
tKHKL
tKH K H
K
tAVKH
WRITE NOP
tKHAX
SA
A1
A2
tIVKH tKHIX
W
tKHIX
D(Data In)
D1-1 D1-2 D2-1 D2-2
A3
D3-1
tD V K H
D3-2
tK H D X
Don ′t Care
Note: 1.D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1, i.e the next internal burst address following A1+ 0.
2. BWx ( NWx ) assumed active.
Undefined
- 14 -
Dec. 2003
Rev 2.0