DS_K7R323682M Datasheet, PDF (8/19 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM

K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR^TM II b2 SRAM
STATE DIAGRAM
POWER-UP
READ NOP
READ
WRITE
WRITE NOP
READ
READ
LOAD NEW
READ ADDRESS
ALWAYS
(FIXED)
DDR READ
READ WRITE
WRITE
LOAD NEW
WRITE ADDRESS
ALWAYS
(FIXED)
WRITE
WRIDTDERPOWRRTITNEOP
Notes : 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "READ" refers to read active status with R=Low, "READ " refers to read inactive status with R=high. "WRITE" and " WRITE" are the same case.
3. Read and write state machine can be active simulateneously.
4. State machine control timing sequence is controlled by K.
-8-
Dec. 2003
Rev 2.0