DS_K7R323682M Datasheet, PDF (18/19 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM

K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR^TM II b2 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
Input High Level
Input Low Level
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
Symbol
VDD
VI H
VIL
VO H
VOL
Min
1.7
1.3
-0.3
1.4
VSS
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
Typ
Max
Unit
1.8
1.9
V
-
V DD+0.3
V
-
0.5
V
-
VDD
V
-
0.4
V
JTAG AC TEST CONDITIONS
Parameter
Input High/Low Level
Input Rise/Fall Time
Input and Output Timing Reference Level
Note: 1. See SRAM AC test output load on page 11.
JTAG AC Characteristics
Parameter
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
JTAG TIMING DIAGRAM
Symbol
VIH/VIL
TR/TF
Symbol
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
Min
1.8/0.0
1.0/1.0
0.9
Min
Max
50
-
20
-
20
-
5
-
5
-
5
-
5
-
5
-
5
-
0
10
Unit
V
ns
V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Note
1
Note
TCK
TMS
TDI
PI
(SRAM)
TDO
tCHCH
tMVCH
tDVCH
tCHMX
tCHCL
tCHDX
tSVCH
tCHSX
tCLQV
tCLCH
- 18 -
Dec. 2003
Rev 2.0