K4S161622E Datasheet, PDF (7/42 Pages) Samsung semiconductor – 1M x 16 SDRAM

K4S161622E
Parameter
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Symbol
tCC(min)
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
-55
5.5
11
16.5
16.5
38.5
55
Version
-60
-70
6
7
12
14
18
20
18
20
42
49
100
60
69
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. Also, supported tRDL=2CLK for - 60 part which is distinguished by bucket code "J".
From the next generation, tRDL will be only 2CLK for every clock frequency.
CMOS SDRAM
Unit
-80
-10
8
10
ns
16
20
ns
20
20
ns
20
20
ns
48
48
ns
us
70
70
ns
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
-55
-60
-70
-80
-10
Symbol
Unit Note
Min Max Min Max Min Max Min Max Min Max
CAS Latency=3
5.5
6
7
8
10
CLK cycle time
tCC
1000
1000
1000
1000
1000 ns 1
CAS Latency=2
-
-
10
10
12
CLK to valid
output delay
CAS Latency=3
-
5
- 5.5 - 5.5 -
6
-
6
tSAC
ns 1, 2
CAS Latency=2
-
6
-
6
-
6
-
6
-8
Output data
tOH
2
- 2.5 - 2.5 - 2.5 - 2.5 - ns 2
CLK high pulse
width
CAS Latency=3
CAS Latency=2
tCH
2
2.5
-
-
3
-
3
- 3.5 - ns 3
3
3
CLK low pulse
width
CAS Latency=3
CAS Latency=2
tCL
2
2.5
-
-
3
-
3
- 3.5 - ns 3
3
3
CAS Latency=3
1.5
1.5
1.75
Input setup time
tSS
-
-
-
2
- 2.5 - ns 3
CAS Latency=2
2
2
2
Input hold time
tSH
1
-
1
-
1
-
1
-
1
- ns 3
CLK to output in Low-Z
tSLZ
1
-
1
-
1
-
1
-
1
- ns 2
CLK to output
in Hi-Z
CAS Latency=3
tSHZ
CAS Latency=2
-
-
5
6
- 5.5 - 5.5
-
6
-
6
-
6
-
6
-
-
6
ns
8
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev 1.1 Jan '03