K4S161622E Datasheet, PDF (35/42 Pages) Samsung semiconductor – 1M x 16 SDRAM

K4S161622E
CMOS SDRAM
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
CLOCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA
A10/AP
Ra
DQ
WE
DQM
Qa0 Qa1 Qa2
Qa3
tSHZ
Qb0 Qb1
Dc0
Dc2
tSHZ
*Note 1
Row Active Read
Clock
Suspension
Read
Read DQM
Write
DQM
Write
Clock
Suspension
Write
DQM
*Note : 1. DQM is needed to prevent bus contention.
: Don't care
Rev 0.2 Oct. '02