K4S161622E Datasheet, PDF (29/42 Pages) Samsung semiconductor – 1M x 16 SDRAM

K4S161622E
Page Read & Write Cycle at Same Bank @Burst Length=4
CMOS SDRAM
CLOCK
CKE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
HIGH
CS
RAS
CAS
tRCD
*Note 2
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A10/AP
Ra
DQ CL=2
Qa0 Qa1 Qb0 Qb1 Qb2
tRDL
Dc0 Dc1 Dd0 Dd1
CL=3
WE
DQM
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0 Dd1
tCDL
*Note 1
*Note 3
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
Precharge
(A-Bank) (A-Bank)
: Don't care
*Note :
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
Rev 0.2 Oct. '02