K4S161622E Datasheet, PDF (19/42 Pages) Samsung semiconductor – 1M x 16 SDRAM

K4S161622E
8. Burst Stop & Interrupted by Precharge
1) Normal Write (BL=4)
CLK
CMD
DQM
DQ
WR
PRE
D0 D1 D2 D3
tRDL Note 1
3) Read Interrupted by Precharge (BL=4)
CLK
CMD
RD
PRE
DQ(CL2)
DQ(CL3)
1
Q0 Q1
Note 3
2
Q0 Q1
CMOS SDRAM
2) Write Burst Stop (BL=8)
CLK
CMD
DQM
DQ
WR
STOP
D0 D1 D2 D3 D4 D5
tBDL Note 2
4) Read Burst Stop (BL=4)
CLK
CMD
RD
DQ(CL2)
DQ(CL3)
STOP
1
Q0 Q1
Note 3
2
Q0 Q1
9. MRS
1) Mode Register Set
CLK
CMD
Note 4
PRE
tRP
MRS
ACT
tMRS = 2CLK
*Note : 1. tRDL : 1 CLK
2. tBDL : 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : Both banks precharge if necessary.
MRS can be issued only at both banks precharge state.
Rev 1.1 Jan '03