K4S161622E Datasheet, PDF (6/42 Pages) Samsung semiconductor – 1M x 16 SDRAM

K4S161622E
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
See Fig. 2
3.3V
Output
870Ω
1200Ω
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
CMOS SDRAM
Z0=50Ω
Unit
V
V
ns
V
Vtt=1.4V
50Ω
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
CAS Latency
CLK cycle time
CL
tCC(min)
Row active to row active delay
tRRD(min)
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to new col.address delay
tCDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
Mode Register Set cycle time
tMRS(min)
Number of valid output
data
CAS Latency=3
CAS Latency=2
-55
32
5.5 10
33
33
77
10 10
-60
32
6 10
32
32
75
10 7
Version
-70
32
7 10
2
32
32
75
100
10 7
1
1
1
1
2
2
1
Unit
-80
-10
3 2 3 2 CLK
8 10 10 12 ns
CLK
3 2 2 2 CLK
3 2 2 2 CLK
6 5 5 4 CLK
us
9 7 7 6 CLK
CLK
CLK
CLK
CLK
CLK
ea
Note
1
1
1
1
1
2, 5
2
2
4
Notes : _{1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then}
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
Rev 1.1 Jan '03