K4S161622E Datasheet, PDF (28/42 Pages) Samsung semiconductor – 1M x 16 SDRAM

K4S161622E
Read & Write Cycle at Same Bank @Burst Length=4
CMOS SDRAM
CLOCK
CKE
CS
RAS
CAS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
tRCD
*Note 1
tRC
HIGH
*Note 2
ADDR
Ra
Ca0
Rb
Cb0
BA
A10/AP
Ra
DQ CL=2
CL=3
tRAC
*Note 3
tRAC
*Note 3
Rb
tOH
Qa0 Qa1 Qa2 Qa3
tSAC
tSHZ *Note 4
tOH
Qa0 Qa1 Qa2 Qa3
tSAC
tSHZ *Note 4
Db0 Db1 Db2 Db3
tRDL
Db0 Db1 Db2 Db3
tRDL
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active Write
(A-Bank) (A-Bank)
Precharge
(A-Bank)
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.
3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst wrap-around).
: Don't care
Rev 0.2 Oct. '02