S5L986F01 Datasheet, PDF (6/35 Pages) Samsung semiconductor – DIGITAL SIGNAL PROCESSOR FOR CDP

S5L9286F01
DIGITAL SIGNAL PROCESSOR FOR CDP
PIN DESCRIPTION (continued)
PIN NO
61
62
63
64
65
66
67
68
69
SYMBOL
XTALSEL
FOK
CDROM
SRAM
TEST1
EFMI
ADATAI
/ISTAT
TRCNT
70
LOCK
71
PBFR
72
SMEF
73
SMON
74
DVDD2
75
SMDP
76
SMDS
77
BCKI
78
TESTV
79
DSPEED
80
LRCHI
IO
DESCRIPTION
I Mode Selection1 (H: 33.8688MHz, L: 16.9344MHz)
I The input for FOK signal of servo
I Mode Selection2 (H: CD-ROM, L: CDP)
I TEST input terminal (GND connection)
I TEST input terminal (GND connection)
I EFM signal input
I Serial audio data input of 48 bit/Slot (MSB first)
O The internal status output
I Tracking counter input signal
Output signal of LKFS condition sampled PBFR/16 (if LKFS is "H", LOCK is "H",
O
if LKFS is sampled "L" at least 8 times by PBFR/16, LOCK is "L".)
O Write frame clock (Lock: 7.35KHz)
O LPF time constant control of the spindle servo error signal
O ON/OFF control signal for spindle servo
- Digital VDD2
O
Spindle Motor drive (Rough control in the SPEED mode, Phase control in the
PHASE mode)
O Spindle Motor drive (Velocity control in the PHASE mode)
I Audio data bit clock input of 48 bit/Slot (2.1168MHz)
I TEST input terminal (GND connection)
I TEST input terminal (VDD connection)
I Channel clock input of 48 bit/Slot (44.1KHz)
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