S5L986F01 Datasheet, PDF (16/35 Pages) Samsung semiconductor – DIGITAL SIGNAL PROCESSOR FOR CDP

S5L9286F01
DIGITAL SIGNAL PROCESSOR FOR CDP
EFM DEMODULATION
The EFM block is composed of the following parts: EFM demodulator to demodulate the EFM signal read from the
disc, EFM phase detector, and the control signal generator.
EFM DEMODULATOR
The modulated 14 channel bit data is demodulated into 8-bit data. There are two types of demodulated data:
subcode data and audio data. Subcode data is input into the subcode handling block, and the audio data is stored
in the internal 16 K SRAM, and its errors are corrected.
EFM PHASE DETECTOR
The EFM signal input from the Disc includes 2.1609 MHz components. To detect the phase of this signal, a Bit
Clock (/PBCK) of 4.3218 MHz is used. PBCK detects the phase of the EFM signals Edge, and sends the results to
the APD0 pin.
VCOI
PBCK
EFMI
EFMD
APDO
1
2
3
(1) When theEFM signal is slower than the VCO signal
(2) When the EFM signal is locked to the VCO signal
(3) When the EFM signal is faster than the VCO signal.
Figure 4. EFM Phase Detector Timing Diagram
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