S5L986F01 Datasheet, PDF (14/35 Pages) Samsung semiconductor – DIGITAL SIGNAL PROCESSOR FOR CDP

S5L9286F01
DIGITAL SIGNAL PROCESSOR FOR CDP
• CNTL-D
This register sets the normal speed and double speed mode.
Bit
3
2
1
0
Identifier
.3
.2
.1
.0
.3 - .0
Speed control
0 0 0 0 Normal Speed
0 0 1 1 Double Speed (2X)
• CNTL-E
This register controls the de-emphasis. .
Bit
3
2
1
0
Identifier
.3
.2
.1
.0
.3 - .0
CLV-servo mode control. Refer to WB of CNTL-W Register.
× × 1 × Internal digital de-emphasis
× × 0 × External analog de-emphasis
NOTE: D1 bit becomes to “L” when reset. MICOM must give the commands of attenuation and mute, when
forward / backward searching. If not, the wrong operation ocurrs easilly during the execution when fast searching.
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