S5L986F01 Datasheet, PDF (13/35 Pages) Samsung semiconductor – DIGITAL SIGNAL PROCESSOR FOR CDP

DIGITAL SIGNAL PROCESSOR FOR CDP
• CNTL-W
Bit
Identifier
WB
WP
GAIN
This register sets the CLV-Servos control period and gain..
3
2
1
0
-
WB
WP
GAIN
Bottom hold period control in speed mode
0 XTFT/32
1 XTFR/16
Peak hold period control in speed mode
0 XTFR/4
1 XTFR/2
SMDS gain control in speed mode
0 - 12 dB
1 0 dB
S5L986F01
• CNTL-C
This register sets the CLV-Servos operating Mode.
D3 — D0
1000
1010
1110
1100
1111
0110
MODE
Forward
Reverse
Speed
Hspeed
Phase
Xphsp
0101
Vphsp
0000
Stop
SMDP
H
L
Speed-mode
Hspeed-mode
Phase-mode
Speed or Phase-mode
Speed or Phase-mode
L
SMSD
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PHASE-MODE
Hi-Z or
PHASE-MODE
Hi-Z or
PHASE-MODE
Hi-Z
SMEF
L
L
L
L
Hi-Z
L, Hi-Z
L, Hi-Z
L
SMON
H
H
H
H
H
H
H
L
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