S5L986F01 Datasheet, PDF (5/35 Pages) Samsung semiconductor – DIGITAL SIGNAL PROCESSOR FOR CDP

DIGITAL SIGNAL PROCESSOR FOR CDP
S5L986F01
PIN DESCRIPTION (continued)
PIN NO
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SYMBOL
SQDT
SQOK
SBCK
SDAT
DVDD1
MUTE
MLT
MDAT
MCK
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
/PBCK
DVSS2
FSDW
ULKFS
/JIT
C4M
C16M
/WE
/CS
IO
DESCRIPTION
O Serial output of Subcode-Q data
O The CRC (Cycle Redundancy Check) check result signal output of Subcode-Q
I Clock for output subcode data
O Subcode serial data output
- Digital VDD1
I Mute control input ("H": Mute ON)
I Latch Signal Input from Micom (Schmit Trigger)
I Serial data input from Micom (Schmit Trigger)
I Serial clock input from Micom (Schmit Trigger)
I/O SRAM data I/O port 8 (MSB)
I/O SRAM data I/O port 7
I/O SRAM data I/O port 6
I/O SRAM data I/O port 5
I/O SRAM data I/O port 4
I/O SRAM data I/O port 3
I/O SRAM data I/O port 2
I/O SRAM data I/O port 1 (LSB)
I/O Monitoring output for error correction (RA0)
I/O Monitoring output for error correction (RA1)
I/O Monitoring output for error correction (RA2)
I/O Monitoring output for error correction (RA3)
I/O Monitoring output for error correction (RA4)
I/O Output of VCO/2 (4.3218MHz) (RA5)
I/O Digital ground 2
I/O Window or unprotected frame sync (RA6)
I/O Frame sync protection state (RA7)
I/O Display of either RAM overflow or underflow for + 4 frame jitter margin (RA8)
I/O Only monitoring signal (4.2336MHz) (RA9)
I/O 16.9344MHz signal output(RA10)
I/O Terminal for test
I/O Terminal for test
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