S5L986F01 Datasheet, PDF (4/35 Pages) Samsung semiconductor – DIGITAL SIGNAL PROCESSOR FOR CDP

S5L9286F01
DIGITAL SIGNAL PROCESSOR FOR CDP
PIN DESCRIPTION
PIN NO
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2
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SYMBOL
AVDD1
DPDO
DPFIN
DPFOUT
CNTVOL
AVSS1
DATX
XIN
XOUT
WDCHO
LRCHO
ADATAO
DVSS1
BCKO
C2PO
VREFL2
VREFL1
AVDD2
RCHOUT
LCHOUT
AVSS2
VREFH1
VREFH2
EMPH
LKFS
S0S1
RESET
/ESP
SQCK
IO
DESCRIPTION
-
Analog VCC1
O Charge pump output for Digital PLL
I
Filter input for Digital PLL
O Filter output for Digital PLL
I
VCO control voltage for Digital PLL
-
Analog Ground1
O Digital Audio output data
I
X'tal oscillator input
O X'tal oscillator output
O Word clock output of 48bit/Slot (88.2kHz)
O Channel clock output of 48 bit/Slot (44.1kHz)
O Serial audio data output of 48 bit/Slot (MSB first)
-
Digital Ground1
O Audio data bit clock output of 48 bit/Slot (2.1168MHz)
O C2 Pointer for output audio data
I
Input terminal2 of reference voltage "L" (Floating)
I
Input terminal1 of reference voltage "L" (GND connection)
-
Analog VCC2
O Right-Channel audio output through D/A converter
O Left-Channel audio output through D/A converter
-
Analog ground2
I
Input terminal1 of reference voltage "H" (VDD connection)
I
Input terminal2 of reference voltage "H" (Floating)
O H: Emphasis ON, L: Emphasis OFF
O The Lock Status output of frame sync
O Output of subcode sync signal(S0+S1)
I
System reset at "L"
I
ESP function ON/OFF control ("L": ESP function ON, "H": ESP function OFF)
I
Clock for output Subcode-Q data
4