S5L986F01 Datasheet, PDF (29/35 Pages) Samsung semiconductor – DIGITAL SIGNAL PROCESSOR FOR CDP

DIGITAL SIGNAL PROCESSOR FOR CDP
S5L986F01
DIGITAL PLL
This device contains Digital PLL in order to obtain the stable channel clock for demodulating EFM signal.
The block diagram of Digital PLL is as follows.
X'tal
Frequency Synthesizer
Phase
Comparator
Low Pass Filter
Voltage
Cotrolled
Oscillator
EFMI
1/N Devider
Digital Main PLL
/PBCK
Figure 16. Digital PLL Circuit Diagram
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