S5L986F01 Datasheet, PDF (18/35 Pages) Samsung semiconductor – DIGITAL SIGNAL PROCESSOR FOR CDP

S5L9286F01
DIGITAL SIGNAL PROCESSOR FOR CDP
SUBCODE BLOCK
The subcode sync signals S0 and S1 are detected in the Subcode sync block. S1 is detected one frame after S0 is
detected. At this time, S0+S1 signal is output to the S0S1 pin, and when the S0S1 signal is high, the S0S1 signal is
output to the SDAT pin. Out of the data input into the EFMI pin, the 14-bit subcode data is EFM demodulated to 8-
bit (P, Q, R, S, T, U, V, W) subcode data, synchronized with the WBCK signal, and output to SDAT by the SBCK
clock. Out of the 8 subcode data, only Q data is stored in the 80 shift registers by the WBCK signal.
If the CRC result is error, low is output to the SQCK pin, and if not, high is output.
If the CNTL-Z registers CRCQ is high, the CRC result is output to the SQDT pin from when the S0 and S1 are high
to SQCKs negative edge. The subcode blocks timing diagram is as follows:
Timing Relation of SQCK, SQDT and S0S1 when SQEN = H
If subcode-Q datas CRCQ is high, the SQOK signal is output to SQDT according to the SQCK, and if CRCQ is low,
the SQOK signal is not output to SQDT.
S0S1
SQOK
SQCK
SQDT
(CRCK=1)
SQDT
(CRCK=0)
SQOK(n)
0
Q4
Q3
Q2
Q1
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q8
Q7
Q6
Q5
Q80
Q79
Q78
Q77
Q80
Q79
Q78
Q77
SQCK(n+1)
0
Q4
Q3
Q4
Q3
Figure 5. Subcode-Q Timing Diagram
Timing Relation of SDAT and SBCK
WBCK
SBCK
a1
2
3
4
5
6
7
8
SDAT
b
Q
R
S
T
U
V
W
C
a) After PBFR goes negative edge, SBCK is set to L for about 10 µs.
b) If S0S1 is L, subcode P is output, and if S0S1 is high, S0S1 is output.
c) If there are more than 7 pulses input into the SBCK pin, the subcode data P, Q, R, S, T,
U, V, and W data are output repeatedly.
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