S5L986F01 Datasheet, PDF (28/35 Pages) Samsung semiconductor – DIGITAL SIGNAL PROCESSOR FOR CDP

S5L9286F01
DIGITAL SIGNAL PROCESSOR FOR CDP
Control Signal
(1) Validity bit: shows the presence of error in 16-bit audio data: “H”=error, “L”=valid data
(2) User definable bit: subcode data out
SOS1
PBFR
SBCK
SBDT
Sync Pattern
P QR S T U VW
Figure 13. Digital Audio Data Out Timing Diagram
(3) Channel status bit: subcode-Qs upper 4-bit data output, shows number of channels, pre-emphasis, copy, CDP-
category, etc.
SOS1
SQDT
PBFR
ID0 ID1 COPY EMPH
Figure 14. Channel Status Data Out Timing Diagram
(4) Parity Bit: makes even parity
L RC H
(44.1KHz)
BCK
(2 .12MH z)
W DC H
(88.2KHz)
ADATA
1
5
10
T
15
20
25
30
35
40
45
50
R-ch (MS B )
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
L-ch (MS B )
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Figure 15. Digital Audio Data Out Timing Diagram 48bits/slot
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