K4H281638L Datasheet, PDF (4/32 Pages) Samsung semiconductor – 128Mb L-die DDR SDRAM Specification

K4H281638L
1.0 Key Features
• V_DD : 2.5V ± 0.2V, V_DDQ : 2.5V ± 0.2V for DDR333, 400
• V_DD : 2.5V ± 5%, V_DDQ : 2.5V ± 5% for DDR500
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR333(2.5 Clock), DDR400(3 Clock), DDR500(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
• 15.6us refresh interval(4K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Lead-Free and Halogen-Free package
• RoHS compliant
DDR SDRAM
2.0 Ordering Information
Part No.
K4H281638L-LCCD
K4H281638L-LCCC
K4H281638L-LCB3
Org.
8M x 16
Max Freq.
CD(DDR500@CL=3)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Interface
Package
SSTL2
66pin TSOP II
Lead-Free & Halogen-Free
Note
3.0 Operating Frequencies
CD(DDR500@CL=3)
Speed @CL2
Speed @CL2.5
Speed @CL3
N/A
166MHz
250MHz
CL-tRCD-tRP
3-4-4
CC(DDR400@CL=3)
N/A
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
N/A
166MHz
-
2.5-3-3
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Rev. 1.2 Feburary 2009