K4H281638L Datasheet, PDF (22/32 Pages) Samsung semiconductor – 128Mb L-die DDR SDRAM Specification

K4H281638L
DDR SDRAM
20.0 AC Timming Parameters & Specifications
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Clock cycle time
CL=2.5
CL=3.0
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge TSOP
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK /CK
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
Power Down Exit
TSOP
Symbol
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tDSS
tDSH
tDQSH
tDQSL
tIS
tIH
tIS
tIH
tHZ
tLZ
tMRD
tDS
tDH
tIPW
tDIPW
tXSNR
tXSRD
tREFI
tQH
tHP
tQHS
tWPST
tRAP
tDAL
tPDEX
CD
(DDR500@CL=3.0)
Min
Max
52
-
60
-
36
70K
16
-
16
-
12
-
12
-
2
-
6
10
4
8
0.45
0.55
0.45
0.55
-0.6
+0.6
-0.6
+0.6
-
0.4
0.9
1.1
0.4
0.6
0.85
1.15
0
-
0.35
-
0.2
-
0.2
-
0.4
-
0.4
-
0.9
-
0.9
-
0.9
-
0.9
-
-0.7
+0.7
-0.7
+0.7
8
-
0.4
-
0.4
-
2.2
-
1.75
-
75
-
200
-
15.6
tHP
-tQHS
-
tCLmin
or tCHmin
-
0.4
0.4
0.6
16
-
(tWR/tCK)
+
-
(tRP/tCK)
1
-
CC
(DDR400@CL=3.0)
Min
55
70
40
15
15
10
15
2
6
5
0.45
0.45
-0.6
-0.7
-
0.9
0.4
0.72
0
0.25
0.2
0.2
0.35
0.35
0.6
0.6
0.7
0.7
-0.65
-0.65
10
0.4
Max
-
-
70K
-
-
-
-
-
10
8
0.55
0.55
+0.6
+0.7
0.4
1.1
0.6
1.28
-
-
-
-
-
-
-
-
-
-
+0.65
+0.65
-
-
0.4
-
2.2
-
1.75
-
75
-
200
-
15.6
tHP
-tQHS
-
tCLmin
or tCHmin
-
0.5
0.4
0.6
15
-
(tWR/tCK)
+
-
(tRP/tCK)
1
-
B3
(DDR333@CL=2.5)
Min
60
72
42
18
18
12
15
1
6
-
0.45
0.45
-0.6
-0.7
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.8
0.8
-0.7
-0.7
12
0.45
Max
-
-
70K
-
-
-
-
-
10
-
0.55
0.55
+0.6
+0.7
0.45
1.1
0.6
1.25
-
-
-
-
-
-
-
-
-
-
+0.7
+0.7
-
-
0.45
-
2.2
1.75
75
200
tHP
-tQHS
tCLmin
or tCHmin
-
-
-
-
15.6
-
-
0.55
0.4
0.6
18
-
(tWR/tCK)
+
-
(tRP/tCK)
1
-
Unit
ns
ns
ns
ns
ns
ns
ns
tCK
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
us
ns
ns
ns
tCK
tCK
tCK
Note
22
13
15, 17~19
15, 17~19
16~19
16~19
11
11
j, k
j, k
18
18
14
21
20, 21
21
12
23
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Rev. 1.2 Feburary 2009