K4H281638L Datasheet, PDF (17/32 Pages) Samsung semiconductor – 128Mb L-die DDR SDRAM Specification

K4H281638L
DDR SDRAM
13.0 DDR SDRAM Spec Items & Test Conditions
Conditions
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK= 6ns for DDR333, 5ns for DDR400, 4ns for DDR500;
DQ,DM and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
Precharge power-down standby current; All banks idle; power - down mode;
CKE = <V_IL(max); tCK=6ns for DDR333, 5ns for DDR400, 4ns for DDR500;
V_IN = V_REF for DQ,DQS and DM.
Precharge Floating standby current; CS > =V_IH(min);All banks idle; CKE > = V_IH(min); tCK=6ns for DDR333, 5ns
for DDR400, 4ns for DDR500; Address and other control inputs changing once per clock cycle; V_IN = V_REF for
DQ,DQS and DM
Precharge Quiet standby current; CS > = V_IH(min); All banks idle;
CKE > = V_IH(min); tCK=6ns for DDR333, 5ns for DDR400, 4ns for DDR500; Address and other control inputs stable
at >= V_IH(min) or =<V_IL(max); V_IN = V_REF for DQ ,DQS and DM
Active power - down standby current ; one bank active; power-down mode;
CKE=< V_IL (max); tCK=6ns for DDR333, 5ns for DDR400, 4ns for DDR500;
V_IN = V_REF for DQ,DQS and DM
Active standby current; CS >= V_IH(min); CKE>=V_IH(min);
one bank active; active - precharge;tCK=6ns for DDR333, 5ns for DDR400, 4ns for DDR500; DQ, DQS and DM
inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control
inputs changing once per clock cycle; CL=2.5 at tCK=6ns for DDR333, CL=3 at tCK=5ns for DDR400, tCK=4ns for
DDR500; 50% of data changing on every transfer; lout = 0 m A
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle; CL=2.5 at tCK=6ns for DDR333, 5ns for
DDR400, tCK=4ns for DDR500; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data chang-
ing at every burst
Auto refresh current; tRC = tRFC(min) which is 12*tCK for DDR333 at tCK=6ns, 14*tCK for DDR400 at tCK=5ns,
15*tCK for DDR500 at tCK=4ns; distributed refresh
Self refresh current; CKE =< 0.2V; External clock on; tCK=6ns for DDR333, 5ns for DDR400, 4ns for DDR500.
Operating current - Four bank operation ; Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
14.0 Input/Output Capacitance
( T_A= 25°C, f=100MHz)
Parameter
Symbol
Min
Max
DeltaCap(max) Unit Note
Input capacitance
(A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
C_IN1
1
4
0.5
pF
4
Input capacitance( CK, CK )
C_IN2
1
5
0.25
pF
4
Data & DQS input/output capacitance
Input capacitance(UDM/LDM for x16)
C_OUT
1
6.5
C_IN3
1
6.5
pF 1,2,3,4
0.5
pF 1,2,3,4
Note :
1. These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameteer is sampled. V_DDQ = +2.5V +0.2V, V_DD = +2.5V+0.2V. For all devices, f=100MHz, tA=25°C, V_OUT(DC) = V_DDQ/2,
V_OUT(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the
board level)
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Rev. 1.2 Feburary 2009