K4H281638L Datasheet, PDF (13/32 Pages) Samsung semiconductor – 128Mb L-die DDR SDRAM Specification

K4H281638L
DDR SDRAM
7.3 Extended Mode Register Set(EMRS)
The extended mode register stores the data for enabling or disabling DLL, and selecting output driver size. The default value of the
extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL.
The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank
precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA1 in the
same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. Two clock cycles are required to complete
the write operation in the extended mode register. The mode register contents can be changed using the same command and clock
cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is
used for EMRS. All the other address pins except A0, A1, A6, A11 and BA0 must be set to low for proper EMRS operation. Refer to the
table for specific codes.
BA1 BA0 A11 A10
A9
A8
*RFU 1 D.I.C
*RFU
A7
A6
A5
D.I.C
A4
A3
*RFU
A2
A1
A0
Address Bus
Extended
D.I.C DLL _{Mode Register}
BA0
0
1
An ~ A0
MRS
EMRS
A11
Vendor ID & Die Status Identi-
fication
0
off
1
on
A6 A1
00
01
11
Output Driver
Impedence Contol
Full
Weak
Matced
*RFU : Should stay " 0" during EMRS cycle.
Figure 7. Extend Mode Register set
A0 DLL Enable
0
Enable
1
Disable
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during powerup initialization, and upon returning to normal
operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enabled
automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Samsung supports a weak driver strength option, intended
for lighter load and/or point-to-point environments. I-V curves for the normal drive strength and weak drive strength are included in
11.1~2 of this document.
MANUFACTURERS VENDOR CODE AND DIE STATUS IDENTIFICATION
The Manufacturers Vendor Code, V, is selected by issuing a EXTENDED MODE REGISTER SET command with bits A11 set to one,
and bits A0-A10 set to the desired values. When the V function is enabled the 128Mb DDR SDRAM will provide its manufacturers vendor
code and die status identification on DQ[1:0].
DQ[1:0]
00
01
10
11
Vendor ID/DSI
Samsung / Pass
Samsung / Fail
Reserved / Pass
Reserved / Fail
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Rev. 1.2 Feburary 2009